Non-temporal load instructions are provided by the SSE extension of the Intel 64 architecture. As kernel code is compiled with SSE extension disabled, this test has been run in user-more.

Interpreted as the address of a cache line. In our tests, different variable are allocated to different cache lines.

It is to be noticed that the new model is stronger that the base model, as the clflushopt instruction is an optimisation of the clflush instruction. In other words, the former enforces less constraints than the latter.

Interpreted as the address of a cache line. In our tests, different variable are allocated to different cache lines.