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AArch64 WRW+WR+posWppteva-tlbi-sync.ishsptevapteoa.va+pos
"Rfe PosRWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAP PosWR Fre"
Variant=imprecise
Cycle=Rfe PosRWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAP PosWR Fre
Relax=[PteVA,TLBI-sync.ISHsWW,PteOA,PteVA]
Safe=Rfe Fre Coe PosWR PosRW
Generator=diy7 (version 7.56+02~dev)
Com=Rf Co Fr
Orig=Rfe PosRWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAP PosWR Fre
{ int x=0; int y=4;
0:X1=x;
1:X0=x; 1:X2=PTE(x); 1:X3=(oa:PA(x), valid:0); 1:X4=(oa:PA(y));
2:X1=x;
}
P0 | P1 | P2 ;
MOV W0,#1 | LDR W1,[X0] | MOV W0,#2 ;
STR W0,[X1] | STR X3,[X2] | STR W0,[X1] ;
| LSR X5,X0,#12 | LDR W2,[X1] ;
| DSB ISH | ;
| TLBI VAAE1IS,X5 | ;
| DSB ISH | ;
| STR X4,[X2] | ;
exists (1:X1=0 /\ 2:X2=1 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=0 /\ 2:X2=1 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=0 /\ 2:X2=1 /\ [x]=1 /\ fault(P2,x,MMU:Translation) /\ ~fault(P0,x) /\ ~fault(P1,x)) \/ (1:X1=0 /\ 2:X2=2 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=0 /\ 2:X2=2 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=0 /\ 2:X2=2 /\ [x]=2 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=0 /\ 2:X2=4 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=0 /\ 2:X2=4 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=1 /\ 2:X2=1 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=1 /\ 2:X2=1 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=1 /\ 2:X2=1 /\ [x]=1 /\ fault(P2,x,MMU:Translation) /\ ~fault(P0,x) /\ ~fault(P1,x)) \/ (1:X1=1 /\ 2:X2=2 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=1 /\ 2:X2=2 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=1 /\ 2:X2=2 /\ [x]=2 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=1 /\ 2:X2=2 /\ [x]=2 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=1 /\ 2:X2=2 /\ [x]=2 /\ fault(P2,x,MMU:Translation) /\ ~fault(P0,x) /\ ~fault(P1,x)) \/ (1:X1=1 /\ 2:X2=4 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=1 /\ 2:X2=4 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=1 /\ 2:X2=4 /\ [x]=2 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=1 /\ 2:X2=4 /\ [x]=2 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=1 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=2 /\ 2:X2=1 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=1 /\ [x]=1 /\ fault(P2,x,MMU:Translation) /\ ~fault(P0,x) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=2 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=2 /\ 2:X2=2 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=2 /\ [x]=1 /\ fault(P2,x,MMU:Translation) /\ ~fault(P0,x) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=2 /\ [x]=2 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=2 /\ [x]=2 /\ fault(P2,x,MMU:Translation) /\ ~fault(P0,x) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=4 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ ~fault(P1,x) /\ ~fault(P2,x)) \/ (1:X1=2 /\ 2:X2=4 /\ [x]=1 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=4 /\ [x]=1 /\ fault(P2,x,MMU:Translation) /\ ~fault(P0,x) /\ ~fault(P1,x)) \/ (1:X1=2 /\ 2:X2=4 /\ [x]=2 /\ fault(P0,x,MMU:Translation) /\ fault(P2,x,MMU:Translation) /\ ~fault(P1,x))