Test R+tlbi-sync.ishsWptevapteoa.va-isbsRpteoa.vap-pos+pos

AArch64 R+tlbi-sync.ishsWptevapteoa.va-isbsRpteoa.vap-pos+pos
"TLBI-sync.ISHsWWPteVAPteOA.VA ISBsWRPteOA.VAP PosRW Coe PosWR FrePPteVA"
Variant=imprecise
Cycle=Coe PosWR FrePPteVA TLBI-sync.ISHsWWPteVAPteOA.VA ISBsWRPteOA.VAP PosRW
Relax=[PteVA,TLBI-sync.ISHsWW,PteOA,PteVA,ISBsWR]
Safe=Fre Coe PosWR PosRW
Generator=diy7 (version 7.56+02~dev)
Com=Co Fr
Orig=TLBI-sync.ISHsWWPteVAPteOA.VA ISBsWRPteOA.VAP PosRW Coe PosWR FrePPteVA
{ int x=0; int y=4;
0:X0=PTE(x); 0:X1=(oa:PA(x), valid:0); 0:X2=(oa:PA(y)); 0:X3=x;
1:X1=x;
}
 P0              | P1          ;
 STR X1,[X0]     | MOV W0,#2   ;
 LSR X6,X3,#12   | STR W0,[X1] ;
 DSB ISH         | LDR W2,[X1] ;
 TLBI VAAE1IS,X6 |             ;
 DSB ISH         |             ;
 STR X2,[X0]     |             ;
 ISB             |             ;
 LDR W4,[X3]     |             ;
 MOV W5,#1       |             ;
 STR W5,[X3]     |             ;
exists (0:X4=4 /\ 1:X2=2 /\ [x]=2 /\ fault(P0,x,MMU:Translation) /\ fault(P1,x,MMU:Translation)) \/ (0:X4=4 /\ 1:X2=2 /\ [x]=2 /\ fault(P1,x,MMU:Translation) /\ ~fault(P0,x))