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AArch64 MP+posWppteva-tlbi-sync.ishsptevapteoa.va+pos
"PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP PosRR Fre"
Variant=imprecise
Cycle=Fre PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP PosRR
Relax=[PteVA,TLBI-sync.ISHsWW,PteOA,PteVA]
Safe=Rfe Fre PosWW PosRR
Generator=diy7 (version 7.56+02~dev)
Com=Rf Fr
Orig=PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP PosRR Fre
{ int x=0; int y=4;
0:X1=x; 0:X2=PTE(x); 0:X3=(oa:PA(x), valid:0); 0:X4=(oa:PA(y));
1:X0=x;
}
P0 | P1 ;
MOV W0,#1 | LDR W1,[X0] ;
STR W0,[X1] | LDR W2,[X0] ;
STR X3,[X2] | ;
LSR X5,X1,#12 | ;
DSB ISH | ;
TLBI VAAE1IS,X5 | ;
DSB ISH | ;
STR X4,[X2] | ;
exists (1:X1=0 /\ 1:X2=0 /\ fault(P1,x,MMU:Translation) /\ ~fault(P0,x)) \/ (1:X1=0 /\ 1:X2=1 /\ fault(P1,x,MMU:Translation) /\ ~fault(P0,x))