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AArch64 R+posWppteva-tlbi-sync.ishsptevapteoa.va+tlbi-sync.ishsWptevapteoa.va-pospteoa.vap
"PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAPteVA TLBI-sync.ISHsWWPteVAPteOA.VA PosWRPteOA.VAP Fre"
Variant=imprecise
Cycle=Fre PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAPteVA TLBI-sync.ISHsWWPteVAPteOA.VA PosWRPteOA.VAP
Relax=[PteVA,TLBI-sync.ISHsWW,PteOA,PteVA]
Safe=Fre Coe PosWW PosWR
Generator=diy7 (version 7.56+02~dev)
Com=Co Fr
Orig=PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAPteVA TLBI-sync.ISHsWWPteVAPteOA.VA PosWRPteOA.VAP Fre
{
pteval_t 0:X6;
int x=0; int y=4;
0:X1=x; 0:X2=PTE(x); 0:X3=(oa:PA(x), valid:0); 0:X4=(oa:PA(y));
1:X0=PTE(x); 1:X1=(oa:PA(y), valid:0); 1:X2=(oa:PA(y)); 1:X3=x;
}
P0 | P1 ;
MOV W0,#1 | STR X1,[X0] ;
STR W0,[X1] | LSR X5,X3,#12 ;
STR X3,[X2] | DSB ISH ;
LSR X5,X1,#12 | TLBI VAAE1IS,X5 ;
DSB ISH | DSB ISH ;
TLBI VAAE1IS,X5 | STR X2,[X0] ;
DSB ISH | LDR W4,[X3] ;
STR X4,[X2] | ;
LDR X6,[X2] | ;
exists (0:X6=(oa:PA(y), valid:0) /\ 1:X4=4 /\ fault(P1,x) /\ ~fault(P0,x))