AArch64 MP+dmb.sy+addr-store-pos-addr+W+PTE
{
int z=1; int a=4;
0:X1=x; 0:X3=y;
1:X0=y; 1:X4=z; 1:X8=x;
2:X0=z;
3:X0=PTE(z); 3:X2=z;
3:X1=(oa:PA(z),valid:0);
3:X3=(oa:PA(a));
}
P0 | P1 | P2 | P3 ;
MOV W0,#1 | MOV W9,#2 | MOV W1,#3 | STR X1,[X0] ;
STR W0,[X1] | STR W9,[X4] | STR W1,[X0] | LSR X4,X2,#12 ;
DMB SY | LDR W1,[X0] | | DSB ISH ;
MOV W2,#1 | AND W2,W1,#64 | | TLBI VAAE1IS,X4 ;
STR W2,[X3] | LDR W3,[X4,W2,SXTW] | | DSB ISH ;
| LDR W5,[X4] | | STR X3,[X0] ;
| AND W6,W5,#128 | | ;
| LDR W7,[X8,W6,SXTW] | | ;
exists (1:X1=0 /\ 1:X3=4 /\ 1:X5=3 /\ 1:X7=0 /\ [z]=2) \/ (1:X1=1 /\ 1:X3=4 /\ 1:X5=3 /\ 1:X7=1 /\ [z]=2)