Test R+posWppteva-tlbi-sync.ishsptevapteoa.va+pos

AArch64 R+posWppteva-tlbi-sync.ishsptevapteoa.va+pos
"PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAP PosWR Fre"
Variant=imprecise
Cycle=Fre PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAP PosWR
Relax=[PteVA,TLBI-sync.ISHsWW,PteOA,PteVA]
Safe=Fre Coe PosWW PosWR
Generator=diy7 (version 7.56+02~dev)
Com=Co Fr
Orig=PosWWPPteVA TLBI-sync.ISHsWWPteVAPteOA.VA CoePteOA.VAP PosWR Fre
{ int x=0; int y=4;
0:X1=x; 0:X2=PTE(x); 0:X3=(oa:PA(x), valid:0); 0:X4=(oa:PA(y));
1:X1=x;
}
 P0              | P1          ;
 MOV W0,#1       | MOV W0,#2   ;
 STR W0,[X1]     | STR W0,[X1] ;
 STR X3,[X2]     | LDR W2,[X1] ;
 LSR X5,X1,#12   |             ;
 DSB ISH         |             ;
 TLBI VAAE1IS,X5 |             ;
 DSB ISH         |             ;
 STR X4,[X2]     |             ;
exists (1:X2=2 /\ [x]=2 /\ fault(P1,x) /\ ~fault(P0,x))