Test MP+tlbi-sync.ishsptevapteoa.va+pos

AArch64 MP+tlbi-sync.ishsptevapteoa.va+pos
"TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP PosRR FrePPteVA"
Variant=imprecise
Cycle=PosRR FrePPteVA TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP
Relax=[PteVA,TLBI-sync.ISHsWW,PteOA,PteVA]
Safe=Rfe Fre PosRR
Generator=diy7 (version 7.56+02~dev)
Com=Rf Fr
Orig=TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP PosRR FrePPteVA
{ int x=0; int y=4;
0:X0=PTE(x); 0:X1=(oa:PA(x), valid:0); 0:X2=(oa:PA(y)); 0:X3=x;
1:X0=x;
}
 P0              | P1          ;
 STR X1,[X0]     | LDR W1,[X0] ;
 LSR X4,X3,#12   | LDR W2,[X0] ;
 DSB ISH         |             ;
 TLBI VAAE1IS,X4 |             ;
 DSB ISH         |             ;
 STR X2,[X0]     |             ;
exists (1:X1=0 /\ 1:X2=0 /\ fault(P1,x))