Test Z6.0+tlbi-sync.ishsptevapteoa.va+pos+pos

AArch64 Z6.0+tlbi-sync.ishsptevapteoa.va+pos+pos
"TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP PosRW Coe PosWR FrePPteVA"
Variant=imprecise
Cycle=Coe PosWR FrePPteVA TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP PosRW
Relax=[PteVA,TLBI-sync.ISHsWW,PteOA,PteVA]
Safe=Rfe Fre Coe PosWR PosRW
Generator=diy7 (version 7.56+02~dev)
Com=Rf Co Fr
Orig=TLBI-sync.ISHsWWPteVAPteOA.VA RfePteOA.VAP PosRW Coe PosWR FrePPteVA
{ int x=0; int y=4;
0:X0=PTE(x); 0:X1=(oa:PA(x), valid:0); 0:X2=(oa:PA(y)); 0:X3=x;
1:X0=x;
2:X1=x;
}
 P0              | P1          | P2          ;
 STR X1,[X0]     | LDR W1,[X0] | MOV W0,#2   ;
 LSR X4,X3,#12   | MOV W2,#1   | STR W0,[X1] ;
 DSB ISH         | STR W2,[X0] | LDR W2,[X1] ;
 TLBI VAAE1IS,X4 |             |             ;
 DSB ISH         |             |             ;
 STR X2,[X0]     |             |             ;
exists (1:X1=4 /\ 2:X2=4 /\ [x]=2 /\ fault(P1,x,MMU:Translation) /\ ~fault(P2,x))