Test MP+posw0w0+posw0q0

AArch64 MP+posw0w0+posw0q0
"PosWWw0w0 Rfew0w0 PosRRw0q0 Freq0w0"
Cycle=Rfew0w0 PosRRw0q0 Freq0w0 PosWWw0w0
Relax=
Safe=Rfew0P PosWWw0P PosRRw0P Freq0P
Prefetch=
Com=Rf Fr
Orig=PosWWw0w0 Rfew0w0 PosRRw0q0 Freq0w0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x1010101; 0:X1=x; 0:X2=0x2020202;
1:X1=x;
}
 P0          | P1          ;
 STR W0,[X1] | LDR W0,[X1] ;
 STR W2,[X1] | LDR X2,[X1] ;
             | LDR X3,[X1] ;
Observed
    x=0x2020202; 1:X3=0x2020202; 1:X2=0x0; 1:X0=0x2020202;