Test MP+posw0q0+posw4w4

AArch64 MP+posw0q0+posw4w4
"PosWWw0q0 Rfeq0w4 PosRRw4w4 Frew4w0"
Cycle=PosWWw0q0 Rfeq0w4 PosRRw4w4 Frew4w0
Relax=
Safe=PosWWw0P Frew4P PosRRw4P Rfeq0P
Prefetch=
Com=Rf Fr
Orig=PosWWw0q0 Rfeq0w4 PosRRw4w4 Frew4w0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 1:X0;

0:X0=0x1010101; 0:X1=x; 0:X2=0x202020202020202;
1:X1=x;
}
 P0          | P1             ;
 STR W0,[X1] | LDR W0,[X1,#4] ;
 STR X2,[X1] | LDR W2,[X1,#4] ;
             | LDR X3,[X1]    ;
Observed
    x=0x202020202020202; 1:X3=0x202020202020202; 1:X2=0x0; 1:X0=0x2020202;