Test R+wsib0h0+rfib0h0

Executions for behaviour: "1:X2=0x203 ; x=0x202"

AArch64 R+wsib0h0+rfib0h0
"Wsib0h0 Wseh0b0 Rfib0h0 Freh0b0"
Cycle=Rfib0h0 Freh0b0 Wsib0h0 Wseh0b0
Relax=Wsib0h0 Freh0b0 Wseh0b0
Safe=Rfib0h0
Generator=diy7 (version 7.52+9(dev))
Prefetch=
Com=Ws Fr
Orig=Wsib0h0 Wseh0b0 Rfib0h0 Freh0b0
{
uint32_t x; uint32_t 1:X2;

0:X1=x;
1:X1=x;
}
 P0           | P1           ;
 MOV W0,#1    | MOV W0,#3    ;
 STRB W0,[X1] | STRB W0,[X1] ;
 MOV W2,#514  | LDRH W2,[X1] ;
 STRH W2,[X1] |              ;
Observed
    x=0x202; 1:X2=0x203;