Test R+wsib0h0+wsib0b0-rfib0h0

Executions for behaviour: "1:X3=0x204 ; x=0x202"

status: 0 real: 0.11 user: 0.10 sys: 0.00 host: limoux

AArch64 R+wsib0h0+wsib0b0-rfib0h0
"Wsib0h0 Wseh0b0 Wsib0b0 Rfib0h0 Freh0b0"
Cycle=Wsib0b0 Rfib0h0 Freh0b0 Wsib0h0 Wseh0b0
Relax=Rfib0h0
Safe=Wsib0b0 Wsib0h0 Freh0b0 Wseh0b0
Generator=diy7 (version 7.52+9(dev))
Prefetch=
Com=Ws Fr
Orig=Wsib0h0 Wseh0b0 Wsib0b0 Rfib0h0 Freh0b0
{
uint32_t x; uint32_t 1:X3;

0:X1=x;
1:X1=x;
}
 P0           | P1           ;
 MOV W0,#1    | MOV W0,#3    ;
 STRB W0,[X1] | STRB W0,[X1] ;
 MOV W2,#514  | MOV W2,#4    ;
 STRH W2,[X1] | STRB W2,[X1] ;
              | LDRH W3,[X1] ;
Observed
    x=0x202; 1:X3=0x204;