Test WWC+addr+dmb.st

ARM WWC+addr+dmb.st
"Rfe DpAddrdW Rfe DMB.STdRW Wse"
Cycle=Rfe DMB.STdRW Wse Rfe DpAddrdW
Prefetch=0:x=F,1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=Rfe DpAddrdW Rfe DMB.STdRW Wse
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1              | P2           ;
 MOV R0,#2    | LDR R0,[%x1]    | LDR R0,[%y2] ;
 STR R0,[%x0] | EOR R1,R0,R0    | DMB ST       ;
              | MOV R2,#1       | MOV R1,#1    ;
              | STR R2,[R1,%y1] | STR R1,[%x2] ;
Observed
    1:R0=1; 2:R0=1; x=1;
and 1:R0=1; 2:R0=1; x=2;