Test ISA2+dmb+dmb.st+addr

ARM ISA2+dmb+dmb.st+addr
"DMBdWW Rfe DMB.STdRW Rfe DpAddrdR Fre"
Cycle=Rfe DMB.STdRW Rfe DpAddrdR Fre DMBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Rf Fr
Orig=DMBdWW Rfe DMB.STdRW Rfe DpAddrdR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0           | P1           | P2              ;
 MOV R0,#1    | LDR R0,[%y1] | LDR R0,[%z2]    ;
 STR R0,[%x0] | DMB ST       | EOR R1,R0,R0    ;
 DMB          | MOV R1,#1    | LDR R2,[R1,%x2] ;
 MOV R1,#1    | STR R1,[%z1] |                 ;
 STR R1,[%y0] |              |                 ;
Observed
    1:R0=1; 2:R0=1; 2:R2=0;