Test MP0106

PPC MP0106
"LwSyncdWW Rfe PodRW PosWR DpCtrlIsyncdR Fre"
Cycle=Rfe PodRW PosWR DpCtrlIsyncdR Fre LwSyncdWW
Relax=[Fre,LwSyncdWW,Rfe]
Safe=PosWR PodRW DpCtrlIsyncdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=LwSyncdWW Rfe PodRW PosWR DpCtrlIsyncdR Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r7=x;
}
 P0           | P1           ;
 li r1,1      | lwz r1,0(r2) ;
 stw r1,0(r2) | li r3,1      ;
 lwsync       | stw r3,0(r4) ;
 li r3,1      | lwz r5,0(r4) ;
 stw r3,0(r4) | cmpw r5,r5   ;
              | beq  LC00    ;
              | LC00:        ;
              | isync        ;
              | lwz r6,0(r7) ;
Observed
    1:r1=1; 1:r6=0;