Test WRW+2W+dmb.st+dsb.st

ARM WRW+2W+dmb.st+dsb.st
"Rfe DMB.STdRW Wse DSB.STdWW Wse"
Cycle=Rfe DMB.STdRW Wse DSB.STdWW Wse
Prefetch=0:x=F,1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Ws Ws
Orig=Rfe DMB.STdRW Wse DSB.STdWW Wse
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1           | P2           ;
 MOV R0,#2    | LDR R0,[%x1] | MOV R0,#2    ;
 STR R0,[%x0] | DMB ST       | STR R0,[%y2] ;
              | MOV R1,#1    | DSB ST       ;
              | STR R1,[%y1] | MOV R1,#1    ;
              |              | STR R1,[%x2] ;
Observed
    1:R0=1; x=1; y=2;
and 1:R0=1; x=2; y=2;
and 1:R0=2; x=2; y=2;