Test SB0030

ARM SB0030
"DMBdWR Fre PosWW PodWW PosWR Fre"
Cycle=Fre PosWW PodWW PosWR Fre DMBdWR
Relax=[Fre,DMBdWR,Fre]
Safe=PosWW PosWR PodWW
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=DMBdWR Fre PosWW PodWW PosWR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 MOV R0,#2    | MOV R0,#1    ;
 STR R0,[%x0] | STR R0,[%y1] ;
 DMB          | MOV R1,#2    ;
 LDR R1,[%y0] | STR R1,[%y1] ;
              | MOV R2,#1    ;
              | STR R2,[%x1] ;
              | LDR R3,[%x1] ;
Observed
    0:R1=0; 1:R3=2; x=2; y=2;
and 0:R1=1; 1:R3=2; x=2; y=2;