Test S0166

ARM S0166
"DMBdWW Rfe PodRW Wse"
Cycle=Rfe PodRW Wse DMBdWW
Relax=[Wse,DMBdWW,Rfe]
Safe=PodRW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWW Rfe PodRW Wse
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 MOV R0,#2    | LDR R0,[%y1] ;
 STR R0,[%x0] | MOV R1,#1    ;
 DMB          | STR R1,[%x1] ;
 MOV R1,#1    |              ;
 STR R1,[%y0] |              ;
Observed
    1:R0=1; x=2;