Test S0153

ARM S0153
"DMBdWW Rfe PodRR DpCtrldW PodWW Wse"
Cycle=Rfe PodRR DpCtrldW PodWW Wse DMBdWW
Relax=[Wse,DMBdWW,Rfe]
Safe=PodWW PodRR DpCtrldW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWW Rfe PodRR DpCtrldW PodWW Wse
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0           | P1           ;
 MOV R0,#2    | LDR R0,[%y1] ;
 STR R0,[%x0] | LDR R1,[%z1] ;
 DMB          | CMP R1,R1    ;
 MOV R1,#1    | BNE LC00     ;
 STR R1,[%y0] | LC00:        ;
              | MOV R2,#1    ;
              | STR R2,[%a1] ;
              | MOV R3,#1    ;
              | STR R3,[%x1] ;
Observed
    1:R0=1; x=2;