Test S0106

ARM S0106
"DMBdWW Rfe PodRR DpDatadW Wse"
Cycle=Rfe PodRR DpDatadW Wse DMBdWW
Relax=[Wse,DMBdWW,Rfe]
Safe=PodRR DpDatadW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWW Rfe PodRR DpDatadW Wse
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0           | P1           ;
 MOV R0,#2    | LDR R0,[%y1] ;
 STR R0,[%x0] | LDR R1,[%z1] ;
 DMB          | EOR R2,R1,R1 ;
 MOV R1,#1    | ADD R2,R2,#1 ;
 STR R1,[%y0] | STR R2,[%x1] ;
Observed
    1:R0=1; x=2;