Test S0072

ARM S0072
"DMBdWW Rfe PodRR DpAddrdR DpAddrdW Wse"
Cycle=Rfe PodRR DpAddrdR DpAddrdW Wse DMBdWW
Relax=[Wse,DMBdWW,Rfe]
Safe=PodRR DpAddrdW DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWW Rfe PodRR DpAddrdR DpAddrdW Wse
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0           | P1              ;
 MOV R0,#2    | LDR R0,[%y1]    ;
 STR R0,[%x0] | LDR R1,[%z1]    ;
 DMB          | EOR R2,R1,R1    ;
 MOV R1,#1    | LDR R3,[R2,%a1] ;
 STR R1,[%y0] | EOR R4,R3,R3    ;
              | MOV R5,#1       ;
              | STR R5,[R4,%x1] ;
Observed
    1:R0=1; x=2;