Test RWC+addr+dsb.st

ARM RWC+addr+dsb.st
"Rfe DpAddrdR Fre DSB.STdWR Fre"
Cycle=Rfe DpAddrdR Fre DSB.STdWR Fre
Prefetch=0:x=T,1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=Rfe DpAddrdR Fre DSB.STdWR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1              | P2           ;
 MOV R0,#1    | LDR R0,[%x1]    | MOV R0,#1    ;
 STR R0,[%x0] | EOR R1,R0,R0    | STR R0,[%y2] ;
              | LDR R2,[R1,%y1] | DSB ST       ;
              |                 | LDR R1,[%x2] ;
Observed
    1:R0=1; 1:R2=0; 2:R1=0;