Test MP0133

ARM MP0133
"DMBdWW Rfe DpDatadW PodWW PosWR Fre"
Cycle=Rfe DpDatadW PodWW PosWR Fre DMBdWW
Relax=[Fre,DMBdWW,Rfe]
Safe=PosWR PodWW DpDatadW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe DpDatadW PodWW PosWR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0           | P1           ;
 MOV R0,#2    | LDR R0,[%y1] ;
 STR R0,[%x0] | EOR R1,R0,R0 ;
 DMB          | ADD R1,R1,#1 ;
 MOV R1,#1    | STR R1,[%z1] ;
 STR R1,[%y0] | MOV R2,#1    ;
              | STR R2,[%x1] ;
              | LDR R3,[%x1] ;
Observed
    1:R0=1; 1:R3=1; x=2;
and 1:R0=1; 1:R3=2; x=2;