Test MP0121

ARM MP0121
"DMBdWW Rfe PodRR DpAddrdW PosWR Fre"
Cycle=Rfe PodRR DpAddrdW PosWR Fre DMBdWW
Relax=[Fre,DMBdWW,Rfe]
Safe=PosWR PodRR DpAddrdW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe PodRR DpAddrdW PosWR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0           | P1              ;
 MOV R0,#2    | LDR R0,[%y1]    ;
 STR R0,[%x0] | LDR R1,[%z1]    ;
 DMB          | EOR R2,R1,R1    ;
 MOV R1,#1    | MOV R3,#1       ;
 STR R1,[%y0] | STR R3,[R2,%x1] ;
              | LDR R4,[%x1]    ;
Observed
    1:R0=1; 1:R4=1; x=2;
and 1:R0=1; 1:R4=2; x=2;