Test MP0101

ARM MP0101
"DMBdWW Rfe PodRR DpAddrdR DpCtrlIsbdR Fre"
Cycle=Rfe PodRR DpAddrdR DpCtrlIsbdR Fre DMBdWW
Relax=[Fre,DMBdWW,Rfe]
Safe=PodRR DpAddrdR DpCtrlIsbdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe PodRR DpAddrdR DpCtrlIsbdR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0           | P1              ;
 MOV R0,#1    | LDR R0,[%y1]    ;
 STR R0,[%x0] | LDR R1,[%z1]    ;
 DMB          | EOR R2,R1,R1    ;
 MOV R1,#1    | LDR R3,[R2,%a1] ;
 STR R1,[%y0] | CMP R3,R3       ;
              | BNE LC00        ;
              | LC00:           ;
              | ISB             ;
              | LDR R4,[%x1]    ;
Observed
    1:R0=1; 1:R4=0;