Test MP+dsb+isb

ARM MP+dsb+isb
"DSBdWW Rfe ISBdRR Fre"
Cycle=Rfe ISBdRR Fre DSBdWW
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 MOV R0, #1    | LDR R0, [%y1] ;
 STR R0, [%x0] | ISB           ;
 DSB           | LDR R1, [%x1] ;
 MOV R1, #1    |               ;
 STR R1, [%y0] |               ;
Observed
    1:R0=1; 1:R1=0;