Test LB0097

ARM LB0097
"DpDatadW Rfe PodRR PosRW Rfe"
Cycle=Rfe PodRR PosRW Rfe DpDatadW
Relax=[Rfe,DpDatadW,Rfe]
Safe=PosRW PodRR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe PodRR PosRW Rfe
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 LDR R0,[%x0] | LDR R0,[%y1] ;
 EOR R1,R0,R0 | LDR R1,[%x1] ;
 ADD R1,R1,#1 | MOV R2,#1    ;
 STR R1,[%y0] | STR R2,[%x1] ;
Observed
    0:R0=1; 1:R0=1;