Test LB0016

ARM LB0016
"DpDatadW Rfe PodRW PodWR DpAddrdW Rfe"
Cycle=Rfe PodRW PodWR DpAddrdW Rfe DpDatadW
Relax=[Rfe,DpDatadW,Rfe]
Safe=PodWR PodRW DpAddrdW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe PodRW PodWR DpAddrdW Rfe
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0           | P1              ;
 LDR R0,[%x0] | LDR R0,[%y1]    ;
 EOR R1,R0,R0 | MOV R1,#1       ;
 ADD R1,R1,#1 | STR R1,[%z1]    ;
 STR R1,[%y0] | LDR R2,[%a1]    ;
              | EOR R3,R2,R2    ;
              | MOV R4,#1       ;
              | STR R4,[R3,%x1] ;
Observed
    0:R0=1; 1:R0=1;