Test LB+dmb+dsb.st

ARM LB+dmb+dsb.st
"DMBdRW Rfe DSB.STdRW Rfe"
Cycle=Rfe DMBdRW Rfe DSB.STdRW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DMBdRW Rfe DSB.STdRW Rfe
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 LDR R0,[%x0] | LDR R0,[%y1] ;
 DMB          | DSB ST       ;
 MOV R1,#1    | MOV R1,#1    ;
 STR R1,[%y0] | STR R1,[%x1] ;
Observed
    0:R0=1; 1:R0=1;