Test CO-RSDWI

Executions for behaviour: "0:R0=0 ; 0:R2=2 ; 0:R3=1 ; z=2"

ARM CO-RSDWI
"Extract uniproc violation from RSDWI"
Prefetch=0:z=W
{
%y0=y; %z0=z;
%z1=z;
}
 P0              | P1           ;
 MOV R9,#1       | MOV R0,#2    ;
 STR R9,[%z0]    | STR R0,[%z1] ;
 LDR R0,[%y0]    |              ;
 EOR R1,R0,R0    |              ;
 LDR R2,[R1,%z0] |              ;
 LDR R3,[%z0]    |              ;
Observed
    0:R0=0; 0:R2=2; 0:R3=1; z=2;