Test MP+dmb+addr-bigdetour4-addr

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; 1:R3=0 ; 1:R5=0 ; 3:R0=0"

Executions for behaviour: "1:R0=1 ; 1:R2=1 ; 1:R3=0 ; 1:R5=0 ; 3:R0=0"

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; 1:R3=1 ; 1:R5=0 ; 3:R0=0"

Executions for behaviour: "1:R0=1 ; 1:R2=1 ; 1:R3=1 ; 1:R5=0 ; 3:R0=0"

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; 1:R3=0 ; 1:R5=0 ; 3:R0=1"

Executions for behaviour: "1:R0=1 ; 1:R2=1 ; 1:R3=0 ; 1:R5=0 ; 3:R0=1"

Executions for behaviour: "1:R0=1 ; 1:R2=1 ; 1:R3=1 ; 1:R5=0 ; 3:R0=1"

ARM MP+dmb+addr-bigdetour4-addr
"DMBdWW Rfe DpAddrdR Leave Fre Rfe DMBdRW Back Rfe DpAddrdR Fre"
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T,3:z=F,3:a=W
Com=Rf Fr Rf Rf
Orig=DMBdWW Rfe DpAddrdR Leave Fre Rfe DMBdRW Back Rfe DpAddrdR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
%z2=z;
%z3=z; %a3=a;
}
 P0           | P1              | P2           | P3           ;
 MOV R0,#1    | LDR R0,[%y1]    | MOV R0,#1    | LDR R0,[%z3] ;
 STR R0,[%x0] | EOR R1,R0,R0    | STR R0,[%z2] | DMB          ;
 DMB          | LDR R2,[R1,%z1] |              | MOV R1,#1    ;
 MOV R1,#1    | LDR R3,[%a1]    |              | STR R1,[%a3] ;
 STR R1,[%y0] | EOR R4,R3,R3    |              |              ;
              | LDR R5,[R4,%x1] |              |              ;
Observed
    1:R0=1; 1:R2=0; 1:R3=0; 1:R5=0; 3:R0=0;
and 1:R0=1; 1:R2=1; 1:R3=0; 1:R5=0; 3:R0=0;
and 1:R0=1; 1:R2=0; 1:R3=1; 1:R5=0; 3:R0=0;
and 1:R0=1; 1:R2=1; 1:R3=1; 1:R5=0; 3:R0=0;
and 1:R0=1; 1:R2=0; 1:R3=0; 1:R5=0; 3:R0=1;
and 1:R0=1; 1:R2=1; 1:R3=0; 1:R5=0; 3:R0=1;
and 1:R0=1; 1:R2=1; 1:R3=1; 1:R5=0; 3:R0=1;