Test MP+dmb+ctrlisb

	Model	Tegra2	APQ8060	A5X	A6X	Exynos5250	Tegra3	Exynos4412	Exynos5410	APQ8064
MP+dmb+ctrlisb	Forbid	No, 0/31G	No, 0/34G	No, 0/11G	No, 0/13G	No, 0/8.3G	No, 0/47G	No, 0/22G	No, 0/6.3G	No, 0/4.5G
		Allow unseen	Allow unseen	Allow unseen	Allow unseen	Allow unseen	Allow unseen	Allow unseen	Allow unseen	Allow unseen

Executions for behaviour: "1:R0=1 ; 1:R1=0"

ARM MP+dmb+ctrlisb
"DMBdWW Rfe DpCtrlIsbdR Fre"
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe DpCtrlIsbdR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 MOV R0,#1    | LDR R0,[%y1] ;
 STR R0,[%x0] | CMP R0,R0    ;
 DMB          | BNE LC00     ;
 MOV R1,#1    | LC00:        ;
 STR R1,[%y0] | ISB          ;
              | LDR R1,[%x1] ;
exists
(1:R0=1 /\ 1:R1=0)