Test R+po+mfence+WT+WB

X86_64 R+po+mfence+WT+WB
"PodWW Coe MFencedWR Fre"
MT=x:WT y:WB
Cycle=Fre PodWW Coe MFencedWR
Relax=MFencedWR
Safe=Fre Coe PodWW
Generator=diy7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Co Fr
Orig=PodWW Coe MFencedWR Fre
Align=
{
}
 P0          | P1            ;
 movl $1,(x) | movl $2,(y)   ;
 movl $1,(y) | mfence        ;
             | movl (x),%eax ;
exists (y=2 /\ 1:rax=0)