Test MP+po+mfence+WB+UC

X86_64 MP+po+mfence+WB+UC
"PodWW Rfe MFencedRR Fre"
MT=x:WB y:UC
Cycle=Rfe MFencedRR Fre PodWW
Relax=MFencedRR
Safe=Rfe Fre PodWW
Generator=diy7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWW Rfe MFencedRR Fre
Align=
{
}
 P0          | P1            ;
 movl $1,(x) | movl (y),%eax ;
 movl $1,(y) | mfence        ;
             | movl (x),%ebx ;
exists (1:rax=1 /\ 1:rbx=0)