Test SB+mfence+po+WT+UC

X86_64 SB+mfence+po+WT+UC
"MFencedWR Fre PodWR Fre"
MT=x:WT y:UC
Cycle=Fre PodWR Fre MFencedWR
Relax=MFencedWR
Safe=Fre PodWR
Generator=diy7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=MFencedWR Fre PodWR Fre
Align=
{
}
 P0            | P1            ;
 movl $1,(x)   | movl $1,(y)   ;
 mfence        | movl (x),%eax ;
 movl (y),%eax |               ;
exists (0:rax=0 /\ 1:rax=0)