Test R+mfence+po+WB+WB

X86_64 R+mfence+po+WB+WB
"MFencedWW Coe PodWR Fre"
MT=x:WB y:WB
Cycle=Fre MFencedWW Coe PodWR
Relax=MFencedWW
Safe=Fre Coe PodWR
Generator=diy7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Co Fr
Orig=MFencedWW Coe PodWR Fre
Align=
{
}
 P0          | P1            ;
 movl $1,(x) | movl $2,(y)   ;
 mfence      | movl (x),%eax ;
 movl $1,(y) |               ;
exists (y=2 /\ 1:rax=0)