Test W+WW+RR+UC+UC

X86_64 W+WW+RR+UC+UC
"Coe PodWW Rfe PodRR Fre"
MT=x:UC,y:UC
Cycle=Rfe PodRR Fre Coe PodWW
Generator=diyone7 (version 7.56+02~dev)
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Co Rf Fr
Orig=Coe PodWW Rfe PodRR Fre
Align=
{
}
 P0          | P1          | P2            ;
 movl $1,(x) | movl $2,(x) | movl (y),%eax ;
             | movl $1,(y) | movl (x),%ebx ;
exists (x=2 /\ 2:rax=1 /\ 2:rbx=0)