X86_64 W+RWC+sfence+po+sfence+WC+WB+WB "SFencedWW Rfe PodRR Fre SFencedWR Fre" MT=x:WC y:WB z:WB Cycle=Rfe PodRR Fre SFencedWR Fre SFencedWW Generator=diyone7 (version 7.56+02~dev) Prefetch=0:x=F,0:y=W,1:y=F,1:z=T,2:z=F,2:x=T Com=Rf Fr Fr Orig=SFencedWW Rfe PodRR Fre SFencedWR Fre Align= { } P0 | P1 | P2 ; movl $1,(x) | movl (y),%eax | movl $1,(z) ; sfence | movl (z),%ebx | sfence ; movl $1,(y) | | movl (x),%eax ; exists (1:rax=1 /\ 1:rbx=0 /\ 2:rax=0)