Test SB+sfences+WB+WB

X86_64 SB+sfences+WB+WB
"SFencedWR Fre SFencedWR Fre"
MT=x:WB y:WB
Cycle=Fre SFencedWR Fre SFencedWR
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=SFencedWR Fre SFencedWR Fre
Align=
{
}
 P0            | P1            ;
 movl $1,(x)   | movl $1,(y)   ;
 sfence        | sfence        ;
 movl (y),%eax | movl (x),%eax ;
exists (0:rax=0 /\ 1:rax=0)