Test S+po+mfence+UC+WC

X86_64 S+po+mfence+UC+WC
"PodWW Rfe MFencedRW Coe"
MT=x:UC y:WC
Cycle=Rfe MFencedRW Coe PodWW
Relax=MFencedRW
Safe=Rfe Coe PodWW
Generator=diy7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Co
Orig=PodWW Rfe MFencedRW Coe
Align=
{
}
 P0          | P1            ;
 movl $2,(x) | movl (y),%eax ;
 movl $1,(y) | mfence        ;
             | movl $1,(x)   ;
exists (x=2 /\ 1:rax=1)