Test S+mfence+po+WB+WC

X86_64 S+mfence+po+WB+WC
"MFencedWW Rfe PodRW Coe"
MT=x:WB y:WC
Cycle=Rfe PodRW Coe MFencedWW
Relax=MFencedWW
Safe=Rfe Coe PodRW
Generator=diy7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Co
Orig=MFencedWW Rfe PodRW Coe
Align=
{
}
 P0          | P1            ;
 movl $2,(x) | movl (y),%eax ;
 mfence      | movl $1,(x)   ;
 movl $1,(y) |               ;
exists (x=2 /\ 1:rax=1)