Test R+sfence+sfence+WT+UC

X86_64 R+sfence+sfence+WT+UC
"SFencedWW Coe SFencedWR Fre"
MT=x:WT y:UC
Cycle=Fre SFencedWW Coe SFencedWR
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Co Fr
Orig=SFencedWW Coe SFencedWR Fre
Align=
{
}
 P0          | P1            ;
 movl $1,(x) | movl $2,(y)   ;
 sfence      | sfence        ;
 movl $1,(y) | movl (x),%eax ;
exists (1:rax=0 /\ [y]=2)