Test Z6.5+sfence+sfence+mfence+WC+WB+WC

X86_64 Z6.5+sfence+sfence+mfence+WC+WB+WC
"SFencedWW Coe SFencedWW Coe MFencedWR Fre"
MT=x:WC y:WB z:WC
Cycle=Fre SFencedWW Coe SFencedWW Coe MFencedWR
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Co Co Fr
Orig=SFencedWW Coe SFencedWW Coe MFencedWR Fre
Align=
{
}
 P0          | P1          | P2            ;
 movl $1,(x) | movl $2,(y) | movl $2,(z)   ;
 sfence      | sfence      | mfence        ;
 movl $1,(y) | movl $1,(z) | movl (x),%eax ;
exists (y=2 /\ z=2 /\ 2:rax=0)