Test Z6.4+sfence+mfence+mfence+UC+WC+WB

X86_64 Z6.4+sfence+mfence+mfence+UC+WC+WB
"SFencedWW Coe MFencedWR Fre MFencedWR Fre"
MT=x:UC y:WC z:WB
Cycle=Fre MFencedWR Fre SFencedWW Coe MFencedWR
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=T,2:z=F,2:x=T
Com=Co Fr Fr
Orig=SFencedWW Coe MFencedWR Fre MFencedWR Fre
Align=
{
}
 P0          | P1            | P2            ;
 movl $1,(x) | movl $2,(y)   | movl $1,(z)   ;
 sfence      | mfence        | mfence        ;
 movl $1,(y) | movl (z),%eax | movl (x),%eax ;
exists (y=2 /\ 1:rax=0 /\ 2:rax=0)