Test Z6.1+sfence+sfence+po+WC+WC+UC

X86_64 Z6.1+sfence+sfence+po+WC+WC+UC
"SFencedWW Coe SFencedWW Rfe PodRW Coe"
MT=x:WC y:WC z:UC
Cycle=Rfe PodRW Coe SFencedWW Coe SFencedWW
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Co Rf Co
Orig=SFencedWW Coe SFencedWW Rfe PodRW Coe
Align=
{
}
 P0          | P1          | P2            ;
 movl $2,(x) | movl $2,(y) | movl (z),%eax ;
 sfence      | sfence      | movl $1,(x)   ;
 movl $1,(y) | movl $1,(z) |               ;
exists (x=2 /\ y=2 /\ 2:rax=1)