Test W+RWC+sfence+po+mfence+WB+WC+UC

X86_64 W+RWC+sfence+po+mfence+WB+WC+UC
"SFencedWW Rfe PodRR Fre MFencedWR Fre"
MT=x:WB y:WC z:UC
Cycle=Rfe PodRR Fre MFencedWR Fre SFencedWW
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=T,2:z=F,2:x=T
Com=Rf Fr Fr
Orig=SFencedWW Rfe PodRR Fre MFencedWR Fre
Align=
{
}
 P0          | P1            | P2            ;
 movl $1,(x) | movl (y),%eax | movl $1,(z)   ;
 sfence      | movl (z),%ebx | mfence        ;
 movl $1,(y) |               | movl (x),%eax ;
exists (1:rax=1 /\ 1:rbx=0 /\ 2:rax=0)