Test SB+mfences+WB+WT

X86_64 SB+mfences+WB+WT
"MFencedWR Fre MFencedWR Fre"
MT=x:WB y:WT
Cycle=Fre MFencedWR Fre MFencedWR
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=MFencedWR Fre MFencedWR Fre
Align=
{
}
 P0            | P1            ;
 movl $1,(x)   | movl $1,(y)   ;
 mfence        | mfence        ;
 movl (y),%eax | movl (x),%eax ;
exists (0:rax=0 /\ 1:rax=0)