Test RWC+po+mfence+WB+WC

X86_64 RWC+po+mfence+WB+WC
"Rfe PodRR Fre MFencedWR Fre"
MT=x:WB y:WC
Generator=diyone7 (version 7.56+02~dev)
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=Rfe PodRR Fre MFencedWR Fre
Align=
{
}
 P0          | P1            | P2            ;
 movl $1,(x) | movl (x),%eax | movl $1,(y)   ;
             | movl (y),%ebx | mfence        ;
             |               | movl (x),%eax ;
exists (1:rax=1 /\ 1:rbx=0 /\ 2:rax=0)