Test S+clflush+mfence+WB+WT

X86_64 S+clflush+mfence+WB+WT
"ClFlushdWW Rfe MFencedRW Coe"
MT=x:WB y:WT
Generator=diyone7 (version 7.56+02~dev)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Co
Orig=ClFlushdWW Rfe MFencedRW Coe
Align=
{
}
 P0          | P1            ;
 movl $2,(x) | movl (y),%eax ;
 clflush (x) | mfence        ;
 movl $1,(y) | movl $1,(x)   ;
exists (x=2 /\ 1:rax=1)